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Physical Design Consultant

Company: Technical Link
Location: San Jose
Posted on: February 17, 2020

Job Description:

Statement of Work: Need for an experienced hierarchical Clock Tree synthesis and implementation expert using Cadence Design Suite. This engineer will assist in the development, implementation and testing of a digital neuromorphic accelerator chip. The selected candidate will work directly with logic designers and system architects to implement ASIC clock tree physical design. Task Description: Candidates are expected to create/modify/script Physical Design tool flows; as well as perform hierarchical clock network synthesis, physical design, timing closure, power/performance/area optimizations and signoff based on the clock specification. Required skills/Level of Experience: Position: Hierarchical chip-level Clock Tree architect. Required Expertise: Multiple successful tapeouts at lower-node technologies (using FinFETs at 14nm nodes and/or below); At least 5 years experience with Cadence tools in the areas of physical design, specifically clock tree synthesis and implementation, including Place and Route, hierarchical integration, signoff; Ability to perform and understand results of STA, timing closure and timing signoff; At least 3 years advanced TCL and SHELL scripting. Ideal candidates will have additional expertise in all of the following areas: Extensive experience with multiple Cadence EDA tools, tool administration, and flow automation; In-depth understanding of memory structures, memory testing and integration; Synthesis (including PLE) and formal equivalence checking; Power/Performance/Area analysis and optimizations; RTL, gate-level and transistor-level simulations and debugging; Ability to create and debug SystemVerilog and UVM; Basic machine learning and neural hardware knowledge; FPGA programming and debugging. Additional Preferred Skills: 3 years of Python scripting; Experience with DFT implementation and integration. . PLEASE NOTE: The candidates must be able to quickly and accurately perform the following tasks: Create/tweak a simple scripted Physical Design flow using Cadence tools on a sample RTL; this flow will include the following steps: synthesis, floorplanning, power-grid creation, CTS, placement, routing, basic signoff; Explain/implement a clock tree in Innovus on a chip-scale canvas with low skew and slew, utilizing via-pillars and multi-cut vias; Perform OCV analysis on the clock tree, generate and parse report files to extract all figures of merit and determine run-to-run differences. - provided by Dice

Keywords: Technical Link, San Jose , Physical Design Consultant, Professions , San Jose, California

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