Sr. System IP Design Verification Engineer - Coherent Interconnect

Company: Samsung Electronics America
Location: San Jose
Posted on: March 16, 2023

Job Description:

Position Summary
Samsung is a world leader in Memory, LCD and System LSI technologies that has the vision and commitment to invest in the future of technology - demonstrated by the $17B investment in the new 3nm Fab in Texas and the commitment to invest in dramatically expanding design activities across GPU, System IP and SoC Architecture. We are currently looking for exceptional Design Verification engineers to join our System IP team in our Austin, TX R & D Center (SARC) and our Advanced Computing Lab (ACL) in San Jose, CA. Our rapidly growing System IP team develops proprietary coherent interconnect and memory controllers deployed in many high volume products. A wealth of growth opportunities for well qualified candidates.
Role and Responsibilities
Role and Responsibilities:
As a Sr. System IP Design Verification Engineer - Coherent Interconnect, you will work as part of a custom system coherent interconnect IP team to drive the functional verification of coherent interconnect, system caching and dynamic memory controllers. This is an individual contributor role with the potential for leadership for well qualified candidates. You will be tasked with formulating, driving and executing the Design Verification plan to ensure the high quality of various sub-blocks of the coherent interconnect and the memory controller IP. Solid background in Design Verification is desired for success.
Key responsibilities include:

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  Work with architects and designers to build verification environments and test plans
  
  
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  Craft functional verification coverage strategy to ensure complete test suite implementation
  
  
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  Develop assertions and checks to optimize isolation time and produce meaningful failing signatures
  
  
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  Analyze failing tests to root cause along, working with RTL and reference modeling teams
  
  
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  Provide input on Architectural and Micro-Architectural specifications for testability and accuracy
  
  
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  Examine code coverage results, identifying exclusions and improving stimulus
  
  
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  Take ownership of key milestone closure by meeting phase gate pass rates, coverage quality, and other quality metrics
  
  
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  Work with RTL to create verification reference models and constrained random stimulus generators
  
  
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  Lead and mentor junior team members
  
  
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  Own test bench, manage tasks and deliverables to meet milestones
  
  
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  Maintain Verification IPs for various bus interfaces
  
  
  Minimum requirements:
  
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    MS Computer Engineering, MSEE, or comparable and 12+ years industry experience in a design verification role
    
    
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    Must have professional experience with Coherent Interconnect, MESI/MOESI protocols
    
    
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    Experience working with Coherency Managers, L3/System-Level Cache, Snoop Filters
    
    
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    Experience working with ARM protocols - AXI, ACE, CHI, APB
    
    
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    Proficient in System Verilog/UVM/OVM, Verdi, and OOP/C++ Deep understanding of constrained randomization and the development of efficient test suites
    
    
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    Experience with code coverage and functional coverage driven verification methodology
    
    
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    Excellent communication skills and be able to work with cross-functional teams to execute verification plan
    
    
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    Proficient RTL skills - can read and understand RTL to create/execute verification plans
    
    
    Skills and Qualifications:
    Preferred candidate will possess the following:
    
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      Energetic, curiosity, and passion in design verification
      
      
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      Good written and verbal communication skills
      
      
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      Knowledge of interconnect and bus protocols - AMBA interconnect experience preferred
      
      
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      Knowledge of memory subsystem design including cache subsystem design
      
      
      Skills and Qualifications
      Compensation for this role will vary among specific regions due to geographic differentials in the labor market, actual pay will be determined considering factors such as relevant skills and experience, and comparisons to other employees in the role. However, compensation in the following regions is expected to be as follows:
      Colorado: Compensation is expected to be between $174,557 to $270,563
      NYC: Compensation is expected to be between $174,557 to $270,563
      Washington State: Compensation is expected to be between $197,041 to $305,414
      California: Compensation is expected to be between $197,041 to $305,414
      Regular full-time employees (salaried or hourly) have access to benefits including: medical, dental, vision, life insurance, 401(k), free onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.
      #SARC
      #ACL
      *This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export controlled information or be eligible to receive a government authorization to access export-controlled information
      
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Keywords: Samsung Electronics America, San Jose , Sr. System IP Design Verification Engineer - Coherent Interconnect, Other , San Jose, California