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Senior SIPI Leader

Company: Lattice Semiconductor
Location: San Jose
Posted on: January 16, 2022

Job Description:

Senior SIPI LeaderTravel Required: Yes

  • This SIPI (Signal Integrity & Power Integrity) Leader will lead our global team on our next-generation FPGAs to ensure signal & power integrity goals are met or exceeded across die, package, and system boards.The leader will have a critical role in coordinating across design, packaging, and board-level development functions in defining methods to assure we meet system-level SIPI requirements and in executing needed simulations to demonstrate requirements are met.
    • Lead a technical SIPI cross functional project team.
    • Provide strategy, methodology definition & technical direction for the cross functional team.
    • Perform signal integrity analysis for package, silicon/die, socket, and boards.
    • Interact with cross-functional teams like silicon circuit design, package design, board design, board fabricators, etc, for ensuring the proper implementation of high-speed interfaces.
    • Define and perform package and system-level Power and Signal Integrity analysis and provide layout optimization recommendation and sign-off of designs.
    • Perform channel margin analysis to provide design trade-offs between die, package, PCB, and interconnect and identify solutions.
    • Analyze and budget SIPI at a multi-component system-level view broken down to detailed signal trace views.
      • Bachelors degree with 7+ years of experience and/or masters degree with 5+ years of experience in Electrical Engineering.
      • Strong problem-solving skills.
      • Strong written and verbal communication skills.
      • Proficient to work in a dynamic and team-oriented environment.
      • Good networking, communication, and influencing skills.
      • Analytical capabilities to interpret simulations and measurement data to identify issues and solutions.
      • In-depth understanding of transmission line theory.
      • Extensive experience in signal integrity, high speed and RF system design, and channel modeling.
      • Experience in the design and analysis of high-speed digital interconnects, such as PCIe, DDR.
      • Experience with silicon devices modeling methods, such as IBIS or Verilog-A.
      • Experience with 2D and 3D field solver tools, such as Cadence PowerSI (3DFEM, XtractIM), Keysight (ADS), iMap, Ansys (HFSS, SiWave), CST.
      • Experience in system simulation including silicon die, package, and PCB.
      • Experience in PCB layout review and associated tools, such as Allegro.
      • Familiar with signal integrity lab measurement equipment and scripting.
      • Experience with signal integrity simulation tools, such as HSpice.
      • Good technical knowledge in PDN.
      • Experience using scripting languages, such as Matlab, Perl, or Python.
      • Experience with high performance advanced package modeling (flip-chip, WLP).
        • Medical, dental, vision effective on date of hire
        • 401(k) with company match
        • Employee Stock Purchase plan, Commuter Benefit, and more
        • Lattice Semiconductor is an EEO/Affirmative Action Employer and does not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, disability, or any other legally protected Jobble

Keywords: Lattice Semiconductor, San Jose , Senior SIPI Leader, Other , San Jose, California

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