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Sr. SOC Design Lead

Company: Lattice Semiconductor
Location: San Jose
Posted on: November 19, 2021

Job Description:

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  • Opportunity.OpportunityDetail.PostedLabel : June 28, 2021 OpportunityDetail.CompanyInformation.Locations Company Profile Lattice Semiconductor (NASDAQ: LSCC) is the global leader in smart connectivity solutions, providing market leading intellectual property and low-power, small form-factor devices that enable more than 8,000 global customers to quickly deliver innovative and differentiated cost and power efficient products. The Company's broad, end-market exposure solves customer problems across the network from the Edge to the Cloud for clients in consumer electronics, industrial equipment, communications infrastructure, computing and automotive. Our technology, long-standing relationships and commitment to world-class support enables our customers to quickly and easily unleash innovative solutions to create a smart, secure and connected world. Our control, connect and compute solutions enable the Internet of Things to operate safely, easily and more autonomously at the edge of the network core. While you may not see our products, you are interacting with them all day, every day. We make your experience smarter and better-connected. Join Team Lattice---and help us continue to drive innovation that creates a smarter, better-connected world. Together, we enable what's next. Job Description This Sr SOC Design Lead will lead our team to define, design and integrate a processor sub-system into our next-generation products. The leader will have a critical role in coordinating across architecture, design and 3 rd party partners to develop our SOC that will be integrated into our next generation platforms. As part of this role, this person will be defining methods to assure that this processor sub-system meets our performance goals and can be verified and tested. Responsibilities
    • Own the design and implementation of the SOC processor sub-system to meet functional, timing, area and power requirements.
    • Drive the crystallization of requirements in collaboration with the Architecture, Systems, Design, Firmware, Verification and Software teams
    • Contribute to project planning by performing Scope/Schedule/Resources tradeoffs
    • Assess overall implementation plan to optimize what will be developed internally and what will be developed by 3 rd party partners
    • Author quality Microarchitecture Documents and conduct reviews
    • Guide and review verification plans for these blocks
    • Author RTL meeting company guidelines and follow up with timing constraints
    • Design and implement logic functions that enable efficient test and debug
    • Specify and Implement Automation to increase design team efficiency
    • Participate in project management for the processor sub-system
    • Perform or drive the synthesis of full-chip netlist and work closely with PnR team Requirements
      • BS with 8+ years of experience or MS with 6+ years of experience in SOC Design
      • At least 5 years of RTL Design experience related to Arm-based SOC Design
      • Have successfully led at least one SOC design/integration effort
      • Excellent verbal and written communication skills
      • Excellent organizational skills and attention to detail
      • Comfortable working with 3 rd party partners
      • Experience executing in parallel projects with rigid schedules
      • Understanding of ARM architecture and AMBA Protocols such as AHB, APB, AXI, ACE, AXI-stream
      • Experience designing with multiple power domains including writing UPF
      • Experience in designing blocks for a SOC
      • Experience in integrating Digital ASIC , Analog IPs and Security IPs into SOC
      • Experiences in integrating high-speed interfaces into SOC, like memory or SERDES
      • Experience with automation using scripting techniques such as PERL, Python or TCL
      • Simulation experience and experience building basic block-level verification suites
      • Experience with synthesis, static timing constraints, analysis & optimization
      • Ability to develop clear and concise engineering documentation
      • Experience in leading-edge SOC development methodologies and tools for SOC integration
      • Experience with industry-standard EDA tools from Cadence, Synopsys or Mentor Desired Qualifications
        • MBIST, LBIST, Scan, Scan Compression, ATPG and JTAG design
        • Experience in designing AI, ML and datacenter acceleration interface(s)
        • Experience in embedded software development flows for firmware development
        • Experience in UVM verification methodology
        • Experience in using HW emulators (FPGA/Veloce/Palladium/Zebu)
        • Working in design teams distributed over multiple sites
        • Post-silicon validation and debug experience
        • FPGA knowledge Competitive benefits package including:
          • Medical, dental, vision effective on date of hire
          • 401(k) with company match
          • Employee Stock Purchase plan, Commuter Benefit, and more Lattice Semiconductor is an EEO/Affirmative Action Employer and does not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, disability or any other legally protected status.

Keywords: Lattice Semiconductor, San Jose , Sr. SOC Design Lead, Other , San Jose, California

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