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Principal Elect Design Engr

Company: Infineon Technologies
Location: San Jose
Posted on: June 9, 2021

Job Description:

If you are an Engineer with between 10-15 years of related semiconductor industry experience, knowledge of ASIC verification methodologies/flows and a proven track record of taking several chips from product definition to production, then this may be the right opportunity for you. Read further to see if this will be your next career move.

In your new role you will:

  • Participate in architecture definition and modeling
  • Contribute to micro-architecture specification and reviews
  • Review industry standard specs and incorporate any changes into the verification plan, to ensure compliance
  • Define verification strategy (constraint random, Formal, Directed etc.) for IP/Chip/System level verification
  • Define and implement verification environment architecture and methodology development
  • Drive block/chip/system level test plan development and execution
  • Work with ASIC designers and architects to produce thoroughly verified, robust IP
  • Oversee all verification for the IP/Chip/System and driving functional and code coverage closure
  • Actively participate in post-silicon bring-up, validation and compliance testing
  • Actively participate in cross functional collaboration with design, software and hardware teams, to ensure a successful product delivery
  • Mentor other engineers and technically guide them

You are best equipped for this task if you have:

  • 10-15 years of related industry experience
  • A proven track record of taking several chips in from product definition to production
  • Good understanding of ASIC design and verification methodologies and flows
  • Solid understanding of standard ASIC verification techniques, including:
  • Test planning
  • Test bench creation
  • Code and Functional coverage
  • Directed and random stimulus generation
  • Assertions
  • Solid understanding of verification methodologies and one or more of the following:
  • Standard testbench languages:
  • SystemVerilog (OVM/UVM)
  • C/C++, Perl, Tcl scripting
  • Verilog PLI

  • Proficiency in object-oriented programming
  • Experience in development of re-suable VIP
  • Experience in working with third party VIP
  • Experience with implementing constraint random verification methodology
  • Good problem solving skills
  • Knowledge of industry standards, such as USB/PCIe is highly desired.
  • Experience with silicon debug, which includes logic and custom Analog Blocks working together
  • Strong written and verbal communication skills
  • The initiative to seek constant improvements in the verification methodologies, and are self-motivated
  • Strong initiative, analytical/problem solving skills
  • A teamwork philosophy and the ability to multitask within a diverse team environment

Keywords: Infineon Technologies, San Jose , Principal Elect Design Engr, Other , San Jose, California

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