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Xilinx: Staff Platform Development Engineer

Company: Xilinx
Location: San Jose
Posted on: September 15, 2020

Job Description:

DescriptionXilinx isSeeking a talented, motivated and self-driven FPGA engineer to be part of theSDAccel platform IP development team. SDAccel is the next generation software programmingEnvironment under the SDx initiative to enable application developers withLittle or no FPGA expertise to use high level programming languages such asOpenCL, C and C to leverage the power of programmable hardware for applicationAcceleration.This high performance team is involved inDevelopment of a scalable, reconfigurableAcceleration platform that can be optimized for machine learning, videoTranscoding, image and speech recognition, CloudRAN, and Big Data analyticsApplications. Candidate will get an opportunity to work on deployment of FPGAsWith Tier1 hyperscale cloud as well as other customers.Responsibilities: End-to-end system level design of the platform including hardware, board, shell design development. Responsibilities will also include integration of hardware, firmware and software and making sure they all work together.FPGA IP integration and testing, board and system hardware bring up of the shell used in acceleration applications in FPGA based PCIe cardsXilinx FPGA design, synthesis, speed and gate optimization, Verilog code development, test bench creation and validation of the designHands-on work involving board bring-up, debugging and validating designs that use PCIeEducation Requirements MS/PhD in Electrical Engineering and minimum 5 years relevant work experience or Bachelor’s degree in Electrical Engineering and 8 years relevant work experience.Required Skills andExperience:Gen3/4, high speed Ethernet networking, DDR3/ DDR4, AXI interconnect and other networking protocols.Define the requirements by working with software and firmware teams to implement complete system level solutionDrive the planning, implementation, architecture and microarchitecture and verification of SDAccel platform featuresVerilog coding and integration, test set up, bench creation and debugFPGA design tool flows, synthesis, timing analysis, partitioning, FPGA programming, bring up and testingKnowledge of timing constraints like Synopsys Design Constraints format.Extensive past experience in FPGA IP integration and testing, board and system hardware bringKnowledge of networking protocols, interfaces and standards like PCIe Gen3/4 and 10G EthernetKnowledge of memory interfaces like DDR3, DDR4Knowledge of AXI interconnect protocolKnowledge of serial protocols like I2C, SPI, JTAGScripting with Tcl, which is the application programming interface for Vivado, and Perl/PythonTeam working skillsAnalytical skillsGood communication and interpersonal skillsAbility to lead a team and coordinate with multiple other teams to drive projects to completionBasic knowledge of C, Linux environmentExperience with Xilinx tools Vivado suiteExperience with high level synthesis and working knowledge of OpenCLPreferred Skills and Experience: Basic knowledge of C, Linux environmentExperience with Xilinx tools Vivado suiteExperience with high level synthesis and working knowledge of OpenCL

Keywords: Xilinx, San Jose , Xilinx: Staff Platform Development Engineer, Other , San Jose, California

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