Xilinx: Senior Mixed Signal Design Engineer

Company: Xilinx
Location: San Jose
Posted on: September 15, 2020

Job Description:

DescriptionAt Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world’s first 5G networks, we empower the world’s builders and visionaries whose ideas solve every day problems and enhance people’s lives.If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters – world class technology that improves the way we live and work. We are ONEXILINX.Job DescriptionBe part of the IP team of next generation PHY/PLL IPsParticipate in defining specification, testing and verification of the IP components. Contribute to micro-architecture specification for SOC/IP AMS blocksParticipate in Analog Mixed Signal IP Architecture specification reviewsHandle complete responsibility of an entire block starting from Micro-architecture specifications, schematic implementation, floor planning, and layout implementation and sign-offWork with and Interact with layout, integration, verification and physical design teams#mhJob QualificationsMS with 2+yrs exp in Electrical Engineering, Computer Science or relatedEquivalentExperience in FinFET & Dual Patterning nodesSuch as 16/14/10/7nmHands-on design experience in performance analogMixed signal circuit blocks such as, IO analog frontend, analog-to-digital(ADC), digital-to-analog (DAC) data converter,, LDO, biasing techniques,Op-amps, interpolator circuits.Experience with the following is a plus: DigitalPLL techniques, TDC or DSP and control theory experience related to digitalPLLs, Dual charge-pump PLL designs, Fractional-N PLLs, spread-spectrum PLLs.Proficient with Cadence custom circuit designTools like ADE-L and ADE-XL and running Monte-Carlo, noise, aging, EM and IRDrop simulations and stability analysis.Experience in low power design techniques forHigh speed/custom digital circuit (e.G. CMOS/CML high speed design forCounters, dividers, …) design and analysis including transistor level timingSign-offSolid understanding of power, area andPerformance trade-offs in mixed signal IP designHave good experience with simulation tools suchAs Spectre, Hspice, AFS, and MATLAB, System Verilog, Python.Capable of understanding DRC and LVS resultsWith verification tools (Calibre, ICV, or like)Proficiency in scripting languages like Perl,Python, matlab etc. is a plus.Able to work effectively in a team, with goodInterpersonal skills, enthusiasm and positive energy High-frequency designExperiencePossess strong analytical/problem solving skillsAnd pronounced attention to detailsMust be a self-starter, and able toIndependently drive tasks to completion

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