RFIC Layout Contractor

Company: Technical Link
Location: San Jose
Posted on: August 3, 2020

Job Description:

Key Qualifications Experience in custom RFanalog layout with extensive knowledge of deep sub-micron CMOS (40nm, 28nm, FinFET, etc.) Knowledgable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing Solid understanding of RC delay, electromigration, and coupling Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE, etc. High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. Knowledge of CADENCE layout tools Excellent communication skills and able to work with cross-functional teams You would also have the following, if you're more experienced Capability to lead other layout engineers for top-level integration Ability to recognize failure prone circuit and layout structures and proactively work with circuit designers for the best approach to resolve problems Scripting skills in PERL or SKILL are a plus, but not required Description As a RF layout engineer, you will be responsible for bull Detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADCDAC, baseband filters, and bandgapbiasLDO. bull Block level and top-level layout through full verification flow including extraction, DRC, LVS, and DFM checking bull Co-work with designers on block level and top-level floorplanning bull Layout review for powergnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling bull Top-level layout integration and verification, schedule management

Keywords: Technical Link, San Jose , RFIC Layout Contractor, Other , San Jose, California