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Principal C++ Software Engineer (R29573/kr)

Company: Cadence Design Systems
Location: San Jose
Posted on: February 24, 2021

Job Description:

Cadence is the leader in hardware emulation-acceleration technologies and products. Our emulation-acceleration system platform is the most advanced industry-leading configurable scalable system, generation after generation, used in labs and datacenters.

We are looking for an exceptional EDA engineer to join the Protium (FPGA Prototyping System) Software Development Team. You will be responsible for the development of new features in the Protium Prototyping Platform. You will work with a small team of super star engineers to develop our next generation FPGA based verification platform. Responsibilities:

  • Develop and enhance the Protium Compiler by implementing new algorithms and optimizations for QoR and performance.
  • Implement new algorithm and enhancements in C/C++ based code to implement the software stack for the platform.
  • Develop the EDA automation flow for the platform with other engineers.
  • Write Design Specifications and Unit Tests for your code
    Position Requirements/Qualifications:
    • At least 6 years of solid experience to back you up.
    • You have a BS/MS/Phd CS,EE,CE
    • Ideally you are a solid contributor in the FPGA or ASIC prototyping/synthesis/verification space and have delivered great QoR on these platforms.
    • You are well renowned for your excellent programming skills in C/C++ and you document your work clearly and love talking about it to your team.
    • You are very comfortable with Verilog or SystemVerilog and understand digital circuits with the ability to write RTL in these languages.
    • Knowledge of using any of the popular simulators and some exposure to multi-threaded/ concurrent programming are pluses.
    • The role requires some digital and exceptional some software skills to be a good match.
    • Practical prior experience of designing, developing strong C/C++ Programming, Algorithms, and familiarity with Verilog/SV and how RTL sequential models are mapped to logic

Keywords: Cadence Design Systems, San Jose , Principal C++ Software Engineer (R29573/kr), IT / Software / Systems , San Jose, California

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