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Design Verification Engineer

Company: Xoriant Corporation
Location: San Jose
Posted on: March 27, 2020

Job Description:

Job Title Design Verification Engineer Location San Jose, CA Duration 6+ months (5+ years of experience is mandatory) Share your resume if you can work on w2, Responsibilities Triage regression failures and make testbench updates Debug functional errors in RTL model using simulation and debug tools Maintain efficient and clean regression status Develop Scalable SystemVerilogUVM testbenches for unit level andor Cluster level verification Review Architecture and Micro-Architecture specifications Closely work with Architects and RTL designers Define, maintain and execute unit level andor Cluster level verification testplans Generate and run Testcases on logic simulation models Code Functional coverage models and System Verilog assertions Drive Functional Coverage and Code coverage to closure Requirements 5 + year s industry experience in a design verification role Proficient in System VerilogUVMOVM, OOPC++ Knowledge of GPU, experience with Shader, Texture, or Memory System a plus Experience with code coverage and functional coverage driven verification methodology Experience in creating, running and debugging of SystemVerilogUVM constraint-random Testbench Excellent working knowledge of scripting languages such as Python or Perl Thanks Regards, Lekha Dhole Desk 408-618-5481

Keywords: Xoriant Corporation, San Jose , Design Verification Engineer, IT / Software / Systems , San Jose, California

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