Engineering Director / SoC Architect - (VLSI / ASIC Design) - Remote, US
Company: Capgemini Engineering
Location: San Jose
Posted on: June 26, 2022
|
|
Job Description:
At Capgemini Engineering you will get to work on industry
leading VLSI technologies and craft innovative solutions to enable
industries/clients in diverse segments like (but not limited to)
AI/ML, Cloud, Datacenter, 5G, computers, communications, mobility,
automotive etc. You will work and partner with the best and
brightest in the field.Summary:As the Chip Architecture Lead for
Pathfinding, you will work with customers directly in the initial
phase of the engagement focusing on 'Tech Readiness' of the program
to be executed. This would include scoping the Architecture
requirements from customer and sizing, resource estimates depending
on technical details, known execution risks and mitigations aligned
with customer. You should be able to lead the functional area
(Architecture) and represent Capgemini Engineering to the customer
and vice versa. Internally you will draw out the program execution
plan and work with implementation leads to draft SOW, milestones.
After the Pathfinding/TR phase, you will own the 'Architecture'
execution for the chip to meet the spec/requirements as aligned
with all the stakeholders.The Chip Architect creates detailed block
design from system requirements and evolving specifications. Works
closely with chip functional leads to meet all functional
requirements, performance, power, and area goals.Role &
Responsibilities: --- Write clear, concise specification for an SoC
including functional and timing descriptions for top level
pins/ports/interfaces, registers and memories, state machines,
data-paths, operating modes, exception/error handling, clocking,
reset, power domains, etc. --- Describe parametric/operating
environment requirements including performance, power, area (PPA)
targets, temperature and process ranges, IO pads, parametric tests,
etc. --- Interact with other system architects to define the
application environment for the SoC being designed (firmware and OS
requirements, external storage devices, sensor/analog components,
etc.) --- Provide SoC (top) level constraints and partitions for
RTL/Logic designers, floorplan & PD engineers, DFT
requirements.Qualifications & Skills Required: --- 15+ years of
relevant experience in Chip/Chiplets Architecture. --- Ability to
define and describe (write specification for) system architecture,
external interfaces, register definitions and operations, major
partitions --- Ability to write clear, concise documents and
diagrams (timing, state machines, register maps, memory
organization, synchronization sequences, etc.) to describe
functional and operational (parametric) aspects of a complex SoC
--- Domain knowledge of various applications and their underlying
hardware requirements (e.g., networking, AI, Machine Learning,
storage devices, IoT) --- Experience in Digital module design and
micro-architecture --- Experienced at modeling complex state
machines, data-paths and bus protocols/high speed (bandwidth)
interfaces such as PCIe --- Understands system level
interactions/optimizations required in addition to Silicon ex:
Package, Interconnect etc.Education:Bachelor's Degree in Electrical
or Computer Engineering or related fieldCapgemini is an Equal
Opportunity Employer encouraging diversity in the workplace. All
qualified applicants will receive consideration for employment
without regard to race, national origin, gender
identity/expression, age, religion, disability, sexual orientation,
genetics, veteran status, marital status or any other
characteristic protected by law.
Keywords: Capgemini Engineering, San Jose , Engineering Director / SoC Architect - (VLSI / ASIC Design) - Remote, US, Executive , San Jose, California
Click
here to apply!
|