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Sr. Principal Engineer, Future Memory Solution

Company: SK hynix America
Location: San Jose
Posted on: July 16, 2019

Job Description:

In this role, you will work with Tier1 SoC engineering teams and customer platform architects as technology partners to develop new memory solutions. You will be an integral member of the technology team to decide on best architectural approach and follow through with SK hynix design implementation. Responsibilities:

  • Collaborate with SoC and Platform architects to understand next-generation memory and storage class memory requirements at the system level.
  • Be a technical leader to define architecture & microarchitecture specification of controller solutions that interface between SOC host controller and emerging memory media.
  • Work with SK hynix designers, FW engineers and verification designers to design and verify controller solutions.
  • Establish co-sim and co-modeling environments with SoC partners to ensure optimal platform level performance and interoperability for new memory solutions. Requirements:
    • BS in Electrical Engineering, Computer Science or related degree required, advanced degrees (MS, PhD) a plus.
    • 10+ years of industry experience in SoC design and background in memory controller design for DRAM memory bus.
    • Knowledge of memory (LPDDRx or DDRx) and high speed IO protocols (PCIe, 802.3). Familiarity with Gen-Z, OpenCAPI, CCIX, NVDIMM-P a plus.
    • Knowledgeable about System Bus architecture and operation (x86, AHB, OCP ).
    • Knowledge of the platform including ACPI, UEFI, MCA and Programming model is a plus
    • Experience with modeling for memory subsystems & use cases (Core - Cache - Home Agent- MC - DIMM + IOHub-IO)
    • Experience with all stages in the ASIC design flow including emulation, prototyping, DFT, timing analysis, floor planning, ECO, bring-up & lab debug, and ATE test development.
    • Knowledge of low-power design methodology, high speed clock distribution and side band protocol (g., SMBUS)
    • Strong working knowledge of Verilog or System Verilog
    • Strong working knowledge of UVM
    • Programming skills in C++ and/or Python, PERL

Keywords: SK hynix America, San Jose , Sr. Principal Engineer, Future Memory Solution, Engineering , San Jose, California

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