Technical Lead Staff Design Verification Engineer - Memory Controller IP

Company: Advanced Micro Devices
Location: San Jose
Posted on: May 28, 2023

Job Description:

WHAT YOU DO AT AMD CHANGES EVERYTHINGWe care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.AMD together we advance_ THE ROLE:
Provide technical leadership and contribution on high speed Memory Controller IP Verification. The individual will help design, develop and use simulation and/or formal based verification environments, at block and full chip FPGA level, to prove the functional correctness of DDR4/5, LPDDR4/5/6, RLD, QDR, and HBM2/3/4 Memory Controller IP designs.
THE PERSON:
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:

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• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
  
• Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
  
• Estimate the time required to write the new feature tests and any required changes to the test environment
  
• Build the directed and random verification tests
  
• Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
  
  
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  • Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements
    
    PREFERRED EXPERIENCE:
    
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    • The ideal candidate is one who has a proven track record on driving strategies and successful verification execution on Memory Controllers (DDR, LPDDR, RLDRAM, QDR, HBM), high performance IPs and/or SOC designs.
      
    • Require hands on experience with verification of state of the art memory controllers such as DDR, LPDDR, RLDRAM and QDR, and HBM. Requires strong understanding of current memory controller protocols and calibration (DDR3/4, LPDDR3/4, RLDRAM3, QDR2, QDRIV, HBM-Gen1/2), JEDEC specification, board skew and jitter modeling.
      
    • Require proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs.
      
    • Candidate is expected to be a strong team player with good communication and leadership skills and one who is able to positively and strategically influence the Memory Controller design teams with an eye towards improving overall product quality.
      
    • Require BS w/ 7+ yrs or MS w/ 5+ yrs or PhD w/ 3+ yrs in Electrical Engineering, Computer Engineering or Computer Science.
      
    • Require experience with development of UVM/OVM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS, Cadence IES to verify memory controller IPs.
      
    • Require strong understanding of state of the art of verification techniques, including assertion and metric-driven verification.
      
    • Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance IP and/or VLSI designs is a plus.
      
    • Require familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management.
      
    • Experience with FPGA programming and software is a plus.
      
    • Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan / VC Formal) is a plus.
      
    • Experience with gate level simulation, power verification, reset verification, contention checking is a plus.
      
    • Experience with silicon debug at the tester and board level, is a plus.
      
      ACADEMIC CREDENTIALS:
      
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      • Bachelors or Masters degree in Electrical Engineering or Computer Engineering
        
        #LI-EM1 At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD's Employee Stock Purchase Plan. You'll also be eligible for competitive benefits described in more detail .AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

Keywords: Advanced Micro Devices, San Jose , Technical Lead Staff Design Verification Engineer - Memory Controller IP, Engineering , San Jose, California