Design Verification Engineer
Company: Wipro Limited
Location: San Jose
Posted on: May 23, 2023
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Job Description:
Job Title: Design Verification Engineer
Duration: Full Time
Location: San Jose , CA---
Description:
Strong knowledge of System Verilog and working knowledge of recent
verification methodologies (UVM)
Domain expertise in one or more of the following areas:
System-on-a-chip verification with multiple CPUs and fixed function
units with AXI or NOC interconnects
Verification of embedded CPUs such as ARM, Tensilica, MIPS CPUs and
interconnect subsystem through C/Assembly language tests
Verification of industry standard serial interfaces such as MIPI,
USB, PCIe using industry standard VIP components
Ethernet Packet Processors, buffer managers, DMA engines etc
PHY layer verification of serial interfaces such as Ethernet, PCIe,
USB etc.
Solid Linux environment skills including the use of Perl, Python or
TCL to write/debug CAD tool scripts.
Keywords: Wipro Limited, San Jose , Design Verification Engineer, Engineering , San Jose, California
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