Lead Design Verification Engineer

Company: Sql Pager LLC
Location: San Jose
Posted on: March 20, 2023

Job Description:

Job Description

• Lead verification efforts on PCIe IPs and SoC products
• Architect and build system and unit-level UVM verification environment
• Work with architects to define verification strategy and execution plans
• Review metrics and deliver task with high quality
• Analyze Functional, Code, and Test Plan Coverage
• Drive and participating in Code Reviews
• Identify, drive, and develop efficiency and IP quality improvement initiatives
• Drive root cause analysis and corrective actions for Functional bugs found in Silicon
• Drive projects from start to the finish and conduct Design verification sign-off Minimal Qualifications
  • Master's degree in Electrical Engineering or related field
  • 5 years of industrial experience in Design Verification
  • Proficiency in SystemVerilog and Object-Oriented Programming
  • Experience in UVM, SVA, VIP, DPI
  • Understand verification best practices
  • Experience in PCIe protocol stack
  • Proficient scripting language in one of: Python, TCL, Shell, Perl
  • Self-motivated team worker Preferred Qualifications
    • Experience of overall design verification experience in the ASIC industry
    • Experience in a design verification lead or management role
    • Strong background in the development of verification environments in System Verilog
    • Expertise in constrained random verification methodologies.
    • Formal verification experience a plus
    • Extensive experience verifying complex designs using UVM
    • Experience in CXL, AXI, AHB, USB, I2C, Ethernet

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