Asic Design Engineer
Company: Cisco
Location: San Jose
Posted on: March 19, 2023
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Job Description:
Responsibilities :
--- Participate in the development of high-performance ASICs from
specification to tape-out, including RTL,
synthesis, physical design, and timing closure
--- Maintain and enhance existing designs using
Verilog/SystemVerilog
--- Participate in the Implementation of new designs using
Verilog/SystemVerilog
--- Triage and troubleshoot failures down to the root cause
--- Actively work with the verification team to deliver ASICs with
high quality
--- Actively work with the physical design team to resolve
implementation and timing issues
--- Develop tests and debug ASICs in the emulation
--- Perform diagnostics and tests for ASICs in the lab
Education and Experience Required :
--- Bachelor's or Master's degree in Electrical Engineering.
--- 4+ years of ASIC design experience.
--- Strong experience with Synthesis, Timing/Power Analysis.
Preferred Qualifications :
--- Experience in design and integration of controllers for high
speed interfaces like PCIE, Ethernet, DDR
--- Experience with ARM protocols (AXI, CHI, APB, AHB) and exposure
to ARM CPU's is a big plus.
- Experience with designing Hardware Accelerators is a big
plus.
--- Hands on experience in Design Verification and/or physical
design is a plus.
--- Familiarity with high performance and low power design
techniques.
Knowledge and Skills :
--- Excellent Verilog, System Verilog programming and debugging
skills.
--- Scripting experience (Python, Perl, TCL, shell
programming).
--- Proficient in synthesis constraints.
--- Ability to write and debug test.
--- Ability to debug system-wide issues.
--- Good written and verbal communication skills.
--- Collaborative and team-focused with the drive to learn and
grow.
Message to applicants applying to work in the U.S.:
When available, the salary range posted for this position reflects
the projected hiring range for new hire, full-time salaries in U.S.
locations, not including equity or benefits. For non-sales roles
the hiring ranges reflect base salary only; employees are also
eligible to receive annual bonuses. Hiring ranges for sales
positions include base and incentive compensation target.
Individual pay is determined by the candidate's hiring location and
additional factors, including but not limited to skillset,
experience, and relevant education, certifications, or training.
Applicants may not be eligible for the full salary range based on
their U.S. hiring location. The recruiter can share more details
about compensation for the role in your location during the hiring
process.
U.S. employees have access to quality medical, dental and vision
insurance, a 401(k) plan with a Cisco matching contribution, short
and long-term disability coverage, basic life insurance and
numerous wellbeing offerings. Employees receive up to twelve paid
holidays per calendar year, which includes one floating holiday,
plus a day off for their birthday. Employees accrue up to 20 days
of Paid Time Off (PTO) each year and have access to paid time away
to deal with critical or emergency issues without tapping into
their PTO. We offer additional paid time to volunteer and give back
to the community. Employees are also able to purchase company stock
through our Employee Stock Purchase Program.
Employees on sales plans earn performance-based incentive pay on
top of their base salary, which is split between quota and
non-quota components. For quota-based incentive pay, Cisco pays at
the standard rate of 1% of incentive target for each 1% revenue
attainment against the quota up to 100%. Once performance exceeds
100% quota attainment, incentive rates may increase up to five
times the standard rate with no cap on incentive compensation. For
non-quota-based sales performance elements such as strategic sales
objectives, Cisco may pay up to 125% of target. Cisco sales plans
do not have a minimum threshold of performance for sales incentive
compensation to be paid.
Keywords: Cisco, San Jose , Asic Design Engineer, Engineering , San Jose, California
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