ASIC Top Level Physical Design Engineer
Location: San Jose
Posted on: January 24, 2023
- Thorough knowledge of the ASIC design timing closure flow and
- Expertise in chip level floor planning
- At least 10+ years hands-on experience in ASIC timing
constraints generation and timing closure
- Expertise in STA tools (such as Primetime) and methodologies
for timing closure with a good understanding of OCV, noise and
cross-talk effects on timing
- Familiarity with all aspects of timing closure of
high-performance, mixed-signal SoCs in advanced process technology
nodes (7nm and below)
- Knowledge of timing corners/modes and process variations
- Knowledge of low-power techniques including clock gating, power
gating and multi-voltage designs
- Proficient in scripting languages (Tcl and Perl)
- Strong communication skills are a pre-requisite as the
candidate will interface with a lot of different groups (e.g.
digital design, verification, DFT, physical design, etc.)
- Self starter and highly motivated
- Familiarity with RTL, synthesis, logic equivalence, DFT, and
backend related methodology and tools
Working with architects, design leads, physical design leads and
package leads, you will develop and to craft and optimize
floorplans during early chip development.
Drive the area review process and collaborate with the ASIC design
team to identify area, interconnect and floorplan improvement
opportunities, solve timing and routing congestion issues with
physical and ASIC design teams by influencing early design and
physical implementation decisions.
You will build tools and improve existing infrastructure to
optimize chip area and speed of execution.
Who We Are
#WeAreCisco, where each person is unique, but we bring our talents
to work as a team and make a difference powering an inclusive
future for all.
We embrace digital, and help our customers implement change in
their digital businesses. Some may think we're "old" (36 years
strong) and only about hardware, but we're also a software company.
And a security company. We even invented an intuitive network that
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we do - you can't put us in a box!
But "Digital Transformation" is an empty buzz phrase without a
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Day to day, we focus on the give and take. We give our best, give
our egos a break, and give of ourselves (because giving back is
built into our DNA.) We take accountability, bold steps, and take
difference to heart. Because without diversity of thought and a
dedication to equality for all, there is no moving forward.
So, you have colorful hair? Don't care. Tattoos? Show off your ink.
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Message to applicants applying to work in the U.S.:
When available, the salary range posted for this position reflects
the projected hiring range for new hire salaries in U.S. locations.
For non-sales roles, the hiring ranges reflect base salary and do
not include bonuses, equity, or benefits. Hiring ranges for sales
positions include base and incentive target, and do not include
equity or benefits. Individual pay is determined by the candidate's
hiring location and additional factors, including but not limited
to skillset, experience, and relevant education, certifications or
training. Applicants may not be eligible for the full salary range
based on their U.S. hiring location. The recruiter can share more
details about compensation for the role in your location during the
Keywords: Cisco, San Jose , ASIC Top Level Physical Design Engineer, Engineering , San Jose, California
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