Senior SoC Design Engineer
Location: San Jose
Posted on: November 26, 2022
Job Description Summary: At Intel we take pride in creating an
energetic and dynamic work environment that is driven by ingenuity
and innovation. We believe the growth and success of our company is
directly linked to the growth and satisfaction of our employees.
That is why Intel is committed to a work environment that is
flexible and collaborative and allows our employees to reach their
Intel is a world leader in programmable logic solutions or FPGAs,
enabling system designers and semiconductor companies to rapidly
and cost effectively innovate, differentiate, and win in their
markets. Intel combines the programmable logic technology
originally invented in 1983 by Altera with software tools,
intellectual property, and customer support to provide high-value
programmable solutions to thousands of customers worldwide.
As a Senior SOC Design Engineer, you will be responsible for the
micro-architecture and design of SoCs and related IPs within the
SoC Design group handling hyperscale computing, configuration, and
security of programmable devices.
Most development happens pre-silicon and requires working closely
with silicon design, firmware, and validation teams for testing and
support. During post silicon phase, engineer is expected to work
with silicon validation team for productization. As a senior member
of the SOC-FPGA Configuration design team, you will be responsible
for the micro-architecture, RTL design and/or integration of SoC
components and IPs.
Core responsibilities will include:
- Work with architects, software engineers, verification
engineers, and physical designers to define and implement the logic
for our unique SOC-FPGA products within a culture of industry
standard best practices and methodologies.
- Designing and writing well-documented, high quality, and
- Working with the Design Verification team to review test plans
and assist in test failure debug.
- Support the post-silicon validation team to define validation
strategies, test plans, quality reviews, and assist with debug when
- Defining timing constraints and working with physical design
engineers for design implementation. Qualifications Minimum
- BS in Computer or Electrical Engineering or equivalent with 10+
years of experience or master's degree with 7 years of experience
in memory technologies.
- Proven industry-track in writing and verifying complex RTL
logic for SOC designs, preferably in Verilog or System
- Experience working with verification engineers on simulation or
emulation flows and familiarity with industry standard verification
methodologies (UVM, Formal, Assertions, Cover points, IPXACT).
- Experience owning and debugging timing constraints, UPF,
synthesis, and driving IP quality checks and releases.
- Experience working with physical design engineers to assist
with the implementation flow, e.g., clock tree synthesis, floor
planning, and implementing ECO fixes.
- Analytical and communication experience and be capable to work
with and influence a globally distributed team.
- Working knowledge and/or experience in integrating hyperscale
computing cores in SoCs (x86, ARM, RISC-V, MIPS).
- Experience in implementing Security design systems with proven
- Experience with performance analysis and integration of cache
coherent and high-performance NOC architectures.
- Experience with clock planning, performance analysis, and
driving physical implementation of complex clocking and reset
- Familiarity with designing/integrating cryptographic,
interface, storage and/or compression IPs will be a plus.
- Experience with cache coherent NOC, high speed peripherals, and
HW-SW programming interface is a plus.
- Experience in advanced low-power design techniques on SoC will
be a plus.
- Experience with post silicon debugging experience is a plus.
Inside this Business Group The Programmable Solutions Group (PSG)
was formed from the acquisition of Altera. As part of Intel, PSG
will create market-leading programmable logic devices that deliver
a wider range of capabilities than customers experience today.
Combining Altera's industry-leading FPGA technology and customer
support with Intel's world-class semiconductor manufacturing
capabilities will enable customers to create the next generation of
electronic systems with unmatched performance and power efficiency.
PSG takes pride in creating an energetic and dynamic work
environment that is driven by ingenuity and innovation. We believe
the growth and success of our group is directly linked to the
growth and satisfaction of our employees. That is why PSG is
committed to a work environment that is flexible and collaborative,
and allows our employees to reach their full potential. Other
Covid Statement Intel strongly encourages employees to be
vaccinated against COVID-19. Intel aligns to federal, state, and
local laws and as a contractor to the U.S. Government is subject to
government mandates that may be issued. Intel policies for COVID-19
including guidance about testing and vaccination are subject to
change over time. Posting Statement All qualified applicants will
receive consideration for employment without regard to race, color,
religion, religious creed, sex, national origin, ancestry, age,
physical or mental disability, medical condition, genetic
information, military and veteran status, marital status,
pregnancy, gender, gender expression, gender identity, sexual
orientation, or any other characteristic protected by local law,
regulation, or ordinance. Benefits We offer a total compensation
package that ranks among the best in the industry. It consists of
competitive pay, stock, bonuses, as well as, benefit programs which
include health, retirement, and vacation. Find more information
about all of our Amazing Benefits here:
Model This role will be eligible for our hybrid work model which
allows employees to split their time between working on-site at
their assigned Intel site and off-site. In certain circumstances
the work model may change to accommodate business needs.
Keywords: Intel, San Jose , Senior SoC Design Engineer, Engineering , San Jose, California
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