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Design Verification Engineer

Company: Capgemini Engineering
Location: San Jose
Posted on: September 22, 2022

Job Description:

Roles/Responsibilities:

Implement a state-of-the-art verification environment to facilitate testing of the RTL against reference MATLAB/C models
Develop detailed test plans and write tests, run regressions, collect coverage matrices, and report progress to the program
Work with the design and Communication systems team and participate in System level verification using test benches constructed using UVM, System C and DPI-C
Develop a highly automated environment to run regressions that can be used to make builds and maintain the sanity of the database

Basic Qualifications:

Bachelor's degree in Electrical / Communications Engineering or Computer Science
5 to 7+ years of experience in verification preferably in communication systems
Proven track record where products have gone to volume production, preferably 1st pass Silicon.
Strong written and verbal skills
Strong problem-solving and debugging skills
Strong proficiency in SystemVerilog, UVM, C, and System C and good scripting skills

Preferred Qualifications:

Master's or Ph.D. degree in Electrical / Communications Engineering
Experience with Verification techniques using MATLAB/C/System reference models
Able to adopt the use of new techniques and methodologies
Experience in developing coverage-driven verification test plans
Familiarity with constrained random and assertion-based verification

This company is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability or veteran status.

Keywords: Capgemini Engineering, San Jose , Design Verification Engineer, Engineering , San Jose, California

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