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DFT Engineer

Company: eInfochips (An Arrow Company)
Location: San Jose
Posted on: August 8, 2022

Job Description:

Get on the einfochips spaceship to boldly go where no engineer has gone before.
Experience range : 8+ year
First Role:--- Senior DFT engineer with good knowledge on ATPG, JTAG and MBIST.--- ATPG pattern generation and test coverage debug using Mentor ATPG tools.--- Scan and OCC chain insertion using Design Compiler.--- RTL and gate level DFT verifications for DFT logic.Any special or skills related notes:--- Hands on experience with Scan (Design Compiler tool) Scan and ATPG (Mentor - Tessent Tool)--- Good knowledge on MBIST and JTAG--- iJTAG and IEEE1500 wrapper understanding.Education: Bachelor's degree in Engineering
Second Role:--- Scan Implementation for large SoC--- MBIST implementation--- ATPG for different fault model and gate level simulation with and w/o SDF--- Understand DFT architecture and able to solve the issues of DFT--- DFX design front-end checks, Spyglass check, CDC checks--- Timing closure support for DFT Test Mode--- Silicon bring-up support and debugging Silicon failuresAny special or skills related notes:--- Hands on experience with Cadence Scan and ATPG tool - Genus and Modus--- Synopsys SMS tool knowledge for MBIST--- iJTAG and IEEE1500 wrapper understanding.
EEO Statement:Einfochips (Arrow) is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status.
Arrow COVID-19 Vaccination Policy:Arrow requires employees to provide proof of full COVID-19 vaccination by:--- December 1, 2021, for all positions located in CO and for business units within immixGroup and Zeus.--- All other employees will be required to identify vaccination status by December 1, 2021, and provide proof of full vaccination by January 3, 2022.

Keywords: eInfochips (An Arrow Company), San Jose , DFT Engineer, Engineering , San Jose, California

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