Lead ASIC Physical Design Engineer
Location: San Jose
Posted on: August 8, 2022
If you are a Lead ASIC Physical Design Engineer with experience,
please read on!
Job Title: Lead ASIC Physical Design Engineer
Job Location: San Jose, CA
Compensation: $150K - $225K base Depending on experience plus stock
We are a small 20-person Smart Interconnect technology company
focused on enabling efficient and performant composable
architectures to enable flexible, scalable, low latency composable
systems. We provide silicon, hardware, and software which leverages
the Compute Express Link (CXL) interconnect standard to provide
high-performance connectivity to a broad ecosystem of components.
We are a next-generation infrastructure company addressing a $500
billion dollar market composed of on-prem, edge data center, and
core data center equipment. We recently raised $17 million in a
Pre-Series A round and are now rapidly expanding.
Top Reasons to Work with Us
- Competitive Compensation ($150K - $225K base Depending on
- Comprehensive Benefits package including stock options!
- The chance to join a small start-up tackling challenging
problems with huge upside potential!
What You Will Be Doing
- Physical design engineer supporting the full chip creation,
layout and final delivery of GDS-2.
- Work with ASIC vendor to drive them for timing closure/STA,
layout, RAS features and on chip repair methodology for the best
solution in the chip industry.
- Develop and own physical design implementation of
multi-hierarchy low-power designs including physical-aware logic
synthesis, design for testability (DFT), floorplan, place and
route, static timing analysis, IR Drop, EM, and physical
verification in advanced technology nodes.
- Resolve design and flow issues related to physical design,
identify potential solutions, and drive execution.
- Deliver multiple ASICs with physical design of an end-to-end
integration of ASIC/SoC design.
What You Need for this Position
Must have a BSEE / MSEE or similar degree with 10-15+ years
experience with the following:
- ASIC Physical Design
- RTL to GDSII flow and design tapeouts in 7nm or below process
- Experience taking multiple ASICs from inception to final
delivery in production
- Low power implementation, power gating, multiple voltage rails,
- EDA tools like DC/Genus, ICC2/Innovus, Primetime,
Redhawk/Voltus or Calibre.
- Running Physical-aware logic synthesis and achieving optimal
synthesis QoR on low power designs.
- Static timing analysis (STA) and concepts, defining timing
constraints and exceptions, corners/voltage definitions.
- Block-level and Full-chip floor-planning and power grid
- Custom or regular clock tree synthesis implementation at block
level or top level, and clock power reduction techniques.
- Python, TCL, Perl programming.
So, if you are a Lead ASIC Physical Design Engineer with
experience, please apply today! or send an updated copy of your
resume to Mike.Vandenbergh@CyberCoders.com for immediate
Email Your Resume In Word To
Looking forward to receiving your resume through our website and
going over the position with you. Clicking apply is the best way to
apply, but you may also:
- Please do NOT change the email subject line in any way. You
must keep the JobID: linkedin : MV1-1684052 -- in the email subject
line for your application to be considered.***
Mike Vandenbergh - Lead Recruiter - CyberCoders
Applicants must be authorized to work in the U.S.
CyberCoders, Inc is proud to be an Equal Opportunity Employer
All qualified applicants will receive consideration for employment
without regard to race, color, religion, sex, national origin,
disability, protected veteran status, or any other characteristic
protected by law.
Your Right to Work - In compliance with federal law, all persons
hired will be required to verify identity and eligibility to work
in the United States and to complete the required employment
eligibility verification document form upon hire.
Keywords: CyberCoders, San Jose , Lead ASIC Physical Design Engineer, Engineering , San Jose, California
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