Design Verification Engineer
Location: San Jose
Posted on: August 7, 2022
- Experience with the latest ASIC verification methodologies,
tools and scripting/programming languages
- Knowledge of & experience with C++
- Self-motivation and the ability to execute effectively without
- Test Content Modification and Debug - In-depth software
knowledge to understand and modify, test content.
- In particular, proficiency with C, C++, and Python are
- Test Case and RTL Hardware Debug - Familiarity with RTL code in
Verilog and how to view and interpret a waveform capture.
- Test Case Execution and Debug - Ability to read and understand
detailed architectural specifications, especially for understanding
test coverage/intent and the debug of system level failures.
Keywords: UST, San Jose , Design Verification Engineer, Engineering , San Jose, California
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