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Low Power Design Engineer - All Level

Company: Qualcomm
Location: San Jose
Posted on: August 5, 2022

Job Description:

General Summary:The Nuvia team is looking for an experienced Engineer to work on leading-edge datacenter SoCs in the area of Low Power design. The Low Power Design Engineer will be responsible for all key aspects of power modeling and analysis, power estimation, optimization and implementation of high performance energy efficient SoC designs.Minimum Qualifications:Bachelor's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, or related work experience. ORMaster's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, or related work experience. ORPhD in Science, Engineering, or related field and 3+ years of ASIC design, verification, or related work experience.
Preferred Qualifications:

  • MS degree in Electrical Engineering with 3 years of practical experience
  • Proficiency in scripting languages (Python/Perl and TCL are highly desirable)
  • Familiarity with System Verilog RTL and simulation
  • Knowledge of major SOC interfaces like PCIE, DRAM as well as infrastructure components like fabrics and memory controllers.
  • Strong problem solving, organizational and communication skills, and ability to work in a dynamic and diverse environment
  • Deep understanding of ASIC low power design techniques
  • Experience in power minimization techniques such as clock gating, power gating, multi-VT design in FINFET process nodes
  • Experience in SoC power modeling and optimization
  • Experience in Power Intent design (UPF), implementation and verification of isolation, level shifters and state retention
  • Experience in low-power verification tools such as PowerArtist and PrimePower

Keywords: Qualcomm, San Jose , Low Power Design Engineer - All Level, Engineering , San Jose, California

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