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Principal/Senior Staff FPGA Design Engineer

Company: InnoPhase
Location: San Jose
Posted on: May 16, 2022

Job Description:

Job DescriptionINNOPHASE is a rapidly growing pre-IPO communications semiconductor company with headquarters in San Diego, CA, and advanced design centers in Irvine, CA, San Jose, CA, Kista, Sweden, and Bangalore, India. We pioneered the industry's lowest power Wi-Fi radio architecture for IoT applications and a revolutionary 5G platform that will transform cellular network deployments. Utilizing our breakthrough, patented, wireless technology we are bringing to market a portfolio of SoCs and modules with a unique value proposition for IoT and 5G applications.Staff FPGA Design Engineer: You will be working with a team of design engineers to develop novel SoC products for connectivity and communications. You will also be a key contributor to product definition and resulting detailed device performance and functional requirements specifications. In addition to delivering high quality digital solutions in the context of the product architecture, the team supports other disciplines with work product such as Verilog stimulus files, test benches for device bring up/characterization, test vectors for product manufacturing, etc.Key Responsibilities

  • Develop multiplatform FPGA design for InnoPhase emulation platforms
  • Develop FPGA design specifications, communicate and verify these specifications with the RF/FW designers
  • Debug designs and provide timely closure
  • Perform Synthesis, P&R and generated FPGA images
  • Bring up emulation platform with SW and system teams
  • Develop and own functional blocks to be used on multiple platforms
  • Hands on debug capability using lab equipment and JTAG
  • Contribute to/review SoC specifications and architectures
  • Front to back digital design and verification – RTL through physical implementation
  • Hands on technical leadership
  • Help define and socialize digital/system design, implementation methodologies and test strategies and flowsJob Requirements
    • MS/PhD EE/CS preferred
    • 15+ years of working with FPGA architecture, implementation and verification
    • Experience with Xilinx and/or Altera tools, TCL, SVN/GIT
    • Experience with embedded systems, wireless protocols, power management, signal processing and standard digital interfaces
    • Deep RTL design knowledge (Verilog/VHDL) and SystemVerilog
    • Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)
    • Proven knowledge of synthesis, static timing, F2B digital SoC design flow
    • Knowledge of languages such as C/C++, Perl, Tcl and Python
    • Strong communication and presentation skills
    • Good skills and interest in mentorship
    • Ability to foresee issues and design in flexibility and workarounds for both known and unknown unknowns
    • Team player with strong sense of urgency to complete projects on timeDesirable Skills
      • Experience with Xilinx Development Toos/Flow
      • Experience lab debugging tools such as JTAG, logic analyzer
      • Able to work effectively with incomplete or changing requirements
      • Good skills an interest in mentorship
      • Strong knowledge of mixed signal concepts
      • Focused, goal driven finisher

Keywords: InnoPhase, San Jose , Principal/Senior Staff FPGA Design Engineer, Engineering , San Jose, California

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