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Layout Engineer

Company: Theery
Location: San Jose
Posted on: May 14, 2022

Job Description:

Qualifications --- Minimum of 5 years of relevant mask design / layout experience ---Deep understanding of analog circuit layout concepts in submicron CMOS technologies ---Experience with Cadence custom circuit design tools - particularly virtuoso Experience running and debugging with verification tools such as Pegasus, Calibre. Experience with FINFET process. Knowledge of DRC and LVS checking flows. Scripting experience is a plus. Responsibilities Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, general I/O's, ESD structures designs in state-of-the-art sub-micron CMOS technologies using Cadence tools Be responsible for floor planning, custom layout and verifying against design rules.

Keywords: Theery, San Jose , Layout Engineer, Engineering , San Jose, California

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