Senior Design Verification Engineer
Location: San Jose
Posted on: May 14, 2022
Job DescriptionINNOPHASE is a rapidly growing pre-IPO
communications semiconductor company with headquarters in San
Diego, CA, and advanced design centers in Irvine, CA, San Jose, CA,
Kista, Sweden, and Bangalore, India. We pioneered the industry's
lowest power Wi-Fi radio architecture for IoT applications and a
revolutionary 5G platform that will transform cellular network
deployments. Utilizing our breakthrough, patented, wireless
technology we are bringing to market a portfolio of SoCs and
modules with a unique value proposition for IoT and 5G
applications.As a Senior Verification Design Engineer, you will
contribute towards our execution and design verification plans of
5G cellular base stations. You will work closely with our
verification team in the US, India and Sweden.Key
- Construct IP, SoC level test benches using verification
components developed at the IP level. Test bench architecture for
random/directed testing, stimulus generation, and checking to
include custom and off the shelf VIP/UVCs.
- Develop and execute verification plans based on design
specifications and collaboration with architects and
- Construct HW/SW Co-Verification
- Be part of a dynamic and functionally diverse team with
opportunities for gaining exposure to modeling (TLM), HW
emulation/acceleration, and SW driven verification.
- Utilize constrained random verification, functional coverage,
code coverage and assertions to achieve goals.Job Requirements
- Master's degree in engineering (or equivalent).
- Five years of experience in design verification - Proven
experience in full chip verification from test plan development to
- Experience constructing chip-level System Verilog and UVM test
bench environments, writing System Verilog Assertions (SVAs), with
embedded software design and test.
- Experience executing block or chip-level verification
- Experience with HW/SW Co-Verification - Developing test
benches, test cases/use-cases, APIs, their execution, and
- Excellent debug skills, with experience debugging RTL in block
and/or chip-level environments.
- Extensive experience with a variety of verification tools and
environments, and a deep understanding of their differences and
capabilities to optimize the right methodology with schedules as
the top priority.
- Experienced in SystemVerilog, UVM, and scripting languages like
Python and Tcl.
- Expertise in using industry standard simulation tools such as
NC Verilog, VCS, QuestaSim, etc.
- Excellent communication skills, energetic and
Keywords: InnoPhase, San Jose , Senior Design Verification Engineer, Engineering , San Jose, California
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