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Senior Staff RTL Design Engineer

Company: Xilinx
Location: San Jose
Posted on: January 16, 2022

Job Description:

Job Description


San Jose, CA, United States

Dec 21, 2021


Job Description

Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx's core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore's Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!

Job Description

Xilinx has an opportunity for an ambitious and exceptionally talented RTL Design Engineer. As a member of our dynamic group, you will have the unique and rewarding opportunity to provide working SerDes design knowledge.

In this job you will be responsible for specifying and/or micro-architecting digital blocks in advanced mixed-signal circuits. You will be also responsible for RTL coding of blocks specified by you or others. You will participate in the design verification and bring-up of such blocks by writing meaningful assertions, debugging code, and otherwise interacting with the design verification team. You will participate in the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc.


Job Qualifications

Education and Experience Requirements

BS 12+ years of exp. MS 8+ years of exp or PhD 5+ years of exp in Electrical Engineer, Computer Engineering or related equivalent

Key Qualifications

  • Good knowledge of mixed signal concepts
  • Good knowledge of RTL design
  • Good knowledge of Verilog and SystemVerilog
  • Good knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)
  • Working knowledge of DFx highly desired
  • Working knowledge of synthesis, static timing
  • Knowledge of scripting languages. Perl and Python are plusses
  • Strong communication and presentation skills
    Xilinx is a US federal government contractor and subcontractor. As required by Executive Order, our US employees are required to be fully vaccinated against COVID-19 regardless of the employees work location or work arrangement (e.g., telework, remote work, etc.), subject to such exceptions as required by law. If selected, you will be required to be vaccinated against COVID-19 and submit documentation of proof of vaccination or have an approved accommodation by December 8, 2021.

    by Jobble

Keywords: Xilinx, San Jose , Senior Staff RTL Design Engineer, Engineering , San Jose, California

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