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Engineer/Sr. Engineer - Physical Design Engineer (Block/SoC APR)

Company: TSMC
Location: San Jose
Posted on: January 16, 2022

Job Description:

Job Location: -San Jose, CaliforniaReports To: -Deputy Technical Director, Design Solution Exploration & Tech Benchmarking
Responsibilities:
-Responsible for physical implementation and tapeout of technology and product development vehicles on TSMC's most advanced process nodes.-Perform the following jobs or tasks:

  • Physical implementation with netlist2GDS flow including block/SOC level floorplan,low power structure, power ground network, placement, clock tree synthesis, routing, design optimization...
  • Design signoff verification including RC extraction, STA, IREM, DRC, LVS, ERC, VCLP.
  • Timing closure, physical design closure, power/signal integrity closure based on the result of
  • signoff verification.
  • Development and evaluation of the methodology and flow to support most advanced process N5/N4/N3 or beyond.
  • CAD development to support design flow and quality monitoring dashboard for with TCLK/TK, CSH, Python.

    Requirements:
    • Education: Bachelor's Degree or above in Electrical Engineering or Computer Science from a top university.
    • At least five 5years of physical implementation experience on RTL2GDS or Netlist2GDS flow.
    • Good communication skills
    • Strong problem solving skills
    • Positive, Active, Collaborative, Self-motivated

      TSMC Technology is an Equal Opportunity Employer.
      -

Keywords: TSMC, San Jose , Engineer/Sr. Engineer - Physical Design Engineer (Block/SoC APR), Engineering , San Jose, California

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