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Physical Design Engineer

Company: Samaritan Technical Professionals
Location: San Jose
Posted on: February 24, 2021

Job Description:

You will be a key member in developing and supporting ASIC Design flow from RTL to GSDII for high-speed networking ASICs.Responsibilities:

  • Architect, develop and support 7nm and lower node(s) place and route flow with multiple library vendors that enables first pass Silicon/ASIC delivery
  • Understand key foundry and IP vendor requirements for next generation place and route flow. Translate these requirements into actionable tasks to implement the place and route flow.
  • Work with EDA vendors (Cadence and Synopsys) to improve overall tool and flow QoR for design needs.Requirements:
    • MSEE with 10 to 15 years of Tool/Flow Development experience in Physical Design. This position requires 10+ years of hands on experience in RTL to GSDII flow implementation and supporting design teams to design closure.
    • Experience in TCL, Python and PERL coding. Ability to debug and fix existing code. Knowledge of version control systems.
    • Experience in macro placement techniques for power, timing and signoff closure.
    • Experience in implementing and evaluating power grid options for next generation ASICs. This should be combined with analysis in Redhawk IR/Voltus toolset to evaluate and analyze various power grid variations and options.
    • Experience in implementing key modules in placement and clock to ensure high density, low power, timing aware placement solutions with minimal clock skews across designs.
    • Support physical design implementation teams in using the flow. Drive and make flow updates that improves QoR (timing, routability, power) based design's needs.
    • Experience in implementing high quality routing modules to ensure DRC, LVS, timing and power closure at the end of the flow. This should assure tight correlation with signoff modules in these categories. Also, ensure good correlation to preroute stages.
    • Experience in setting up signoff extraction using STARRC and QRC with detailed understanding of various options in each tool to achieve correlation between full chip and block flows.
    • Experience with PrimeTime based power and timing closure flows.
    • Experience in full chip context timing or hierarchical timing of block flows to ensure faster timing closure turnaround.

Keywords: Samaritan Technical Professionals, San Jose , Physical Design Engineer, Engineering , San Jose, California

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