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Layout Engineer

Company: TSMC
Location: San Jose
Posted on: February 23, 2021

Job Description:

Responsibilities:

  • SRAM memory compiler layout (bit cell, pitch cell, IO & logic).
  • Signals and Power buses planning.
  • Hook up from leaf cell to top level & floor planning.
  • Memory layout is a plus. Requirements:
    • Education:
    • Associates (AA) or equivalent of 5 years direct memory experience with hands-on layout methodology and tools, Cadence, Caliber verification (DRC, LVS, Antenna, etc.).
    • Also welcome new Bachelor graduates.
    • Experience in advance technology (N10, N7) layout preferred.
    • Strong interpersonal and communication skills.
    • Highly organized and detailed oriented. TSMC Technology Inc. is an Equal Opportunity Employer.

Keywords: TSMC, San Jose , Layout Engineer, Engineering , San Jose, California

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