SanJoseCARecruiter Since 2001
the smart solution for San Jose jobs

RTL Design Engineer

Company: HPC Americas Consulting LLC
Location: San Jose
Posted on: November 23, 2020

Job Description:

Lead RTL Design Engineer We have below full-time position with our client in San Jose, CA Pls send your resume with your salary expectation and current location. mailto Need someone with RTL experience who also has concept of timing closure, STA flow and concept, DFT methodologies and exposure to high-speed designs. Job Description This is an opportunity to contribute and innovate in the design of next-generation Memory subsystem Design IPs. As a core member of the PHY Design team, your responsibilities will span across various aspects for the ASIC frontend flow, which includes developing micro-architecturedesign specifications, implementing RTL code for complex digital logics, RTL integration, synthesizing and optimizing the design for better timing, PPA, doing performance analysis, setting up block level test bench, collaborating with the verification team and analyzing the coverage results. You will also be responsible for interfacing with the Physical Design team on STA, timing closure and PR, and participating in silicon bring up with the validation team. You will be working and interacting with accomplished digital and analog circuit designers. You will work in a dynamic, team environment and must be an effective team player on projects. You will have ample opportunities to expand your knowledge, expertise and skillset. You would also be contributing to futuristic clocking architecture, design micro-architecture and RTL design decisions targeted at better timing, PPA, based on pre and post implementation timing analysis. This is an opportunity to work and interact with accomplished digital and analog circuit designers and timing experts who has built industry leading multi-protocol memory PHYs for over a decade. Desired Qualifications. Prior experience in timing and or RTL design of high-speed interfaces. Prior experience of collaborating with Physical Design teams in multiple successful ASICIP tapeouts. Knowledge of the IPSoC level timing closure flow and methodology. Good command of VerilogSystem Verilog language Command of Simulation, Lint, Synthesis, STA, formal verification, functional coverage, design for test, and design methodologies Ability to handle multiple projectstasks successfully Experience in IPASIC timing constraints generation. Expertise in STA tools and flow Hands on experience in timing constraints generation and management Proficiency in scripting languages (TCL and Perl) Familiarity with synthesis, logic equivalence, DFT and backend related methodology and tools Background in Constraint analysis and debug, using industry standard tools. Understanding and experience in timing closure of various test modes such as scan shift, scan capture, atspeed and BIST testing. Desired skills Knowledge of DDRGDDR DRAM protocol high-speed PHYs Experience designing or integrating IP Experience in high speed and low power digital design using advanced deep micron process. Experience with highly configurable designs

Keywords: HPC Americas Consulting LLC, San Jose , RTL Design Engineer, Engineering , San Jose, California

Click here to apply!

Didn't find what you're looking for? Search again!

I'm looking for
in category
within


Other Engineering Jobs


Mid-Market, Solutions Engineer
Description: You will play a critical role in helping our prospects understand the value of Asana. Through your deep product knowledge, expertise in how companies use and deploy SaaS applications, and technical objection (more...)
Company: Asana
Location: San Francisco
Posted on: 11/24/2020

Diesel Mechanic
Description: JOB SUMMARY:Diesel and gas service technicians and mechanics inspect, repair, or overhaul trucks, and anything else with a diesel or gas engine and other rolling equipment for the company. Performs mechanical (more...)
Company: Biagi Bros Transportation
Location: American Canyon
Posted on: 11/24/2020

Support Engineer
Description: Facebook's mission is to give people the power to build community and bring the world closer together. Through our family of apps and services, we're building a different kind of company that connects (more...)
Company: Facebook
Location: San Francisco
Posted on: 11/24/2020


Data Engineer
Description: Data Engineer The data team designs, implements and scales data pipelines that transform raw data into actionable models and metrics that enable insight. This team owns the pipelines that transport and (more...)
Company: Asana
Location: San Francisco
Posted on: 11/24/2020

Principal Engineer/Architect - Telemetry Data Platform(Open to Remote)
Description: Your OpportunityWe are looking for an experienced software engineer and technical leader to join our architecture team. Members of our group work closely with engineering teams, product managers, and (more...)
Company: New Relic
Location: San Francisco
Posted on: 11/24/2020

Cloud Services Engineer
Description: U.S. Citizens and those authorized to work in the U.S are encouraged to apply. We are unable to sponsor at this time. Assignment location preference is San Francisco, CA however candidates located in (more...)
Company: TA Digital
Location: San Francisco
Posted on: 11/24/2020

91B Light-Wheel Vehicle Mechanic
Description: As a Light-Wheel Vehicle Mechanic for the Army National Guard you'll ensure that anything that moves on wheels is ready to hit the road. In this role, you will primarily be responsible for supervising (more...)
Company: Army National Guard
Location: Sacramento
Posted on: 11/24/2020

91B Light-Wheel Vehicle Mechanic
Description: As a Light-Wheel Vehicle Mechanic for the Army National Guard you'll ensure that anything that moves on wheels is ready to hit the road. In this role, you will primarily be responsible for supervising (more...)
Company: Army National Guard
Location: Benicia
Posted on: 11/24/2020

Junior Civil Engineer (Civil Land Development Industry)
Description: Position: Junior to Associate Level Civil Engineer Civil Engineering Land Development Experienced Office Locations: Folsom or Sacramento California Term: Full Time Permanent Employment Compensation: (more...)
Company: TJG Civil Engineers and Land Planners
Location: Sacramento
Posted on: 11/24/2020

Automation Test Engineer CPO
Description: Automation Test Engineer - CPO Federal Reserve Bank of San Francisco CA-San Francisco Full-time Regular Exempt Experienced Yes, 10 of the Time Day Job Tier II - No Credit Check The Cash Product Office (more...)
Company: Federal Reserve Bank of Richmond
Location: San Francisco
Posted on: 11/24/2020

Log In or Create An Account

Get the latest California jobs by following @recnetCA on Twitter!

San Jose RSS job feeds