RTL Design Engineer

Company: HPC Americas Consulting LLC
Location: San Jose
Posted on: November 23, 2020

Job Description:

Lead RTL Design Engineer We have below full-time position with our client in San Jose, CA Pls send your resume with your salary expectation and current location. mailto Need someone with RTL experience who also has concept of timing closure, STA flow and concept, DFT methodologies and exposure to high-speed designs. Job Description This is an opportunity to contribute and innovate in the design of next-generation Memory subsystem Design IPs. As a core member of the PHY Design team, your responsibilities will span across various aspects for the ASIC frontend flow, which includes developing micro-architecturedesign specifications, implementing RTL code for complex digital logics, RTL integration, synthesizing and optimizing the design for better timing, PPA, doing performance analysis, setting up block level test bench, collaborating with the verification team and analyzing the coverage results. You will also be responsible for interfacing with the Physical Design team on STA, timing closure and PR, and participating in silicon bring up with the validation team. You will be working and interacting with accomplished digital and analog circuit designers. You will work in a dynamic, team environment and must be an effective team player on projects. You will have ample opportunities to expand your knowledge, expertise and skillset. You would also be contributing to futuristic clocking architecture, design micro-architecture and RTL design decisions targeted at better timing, PPA, based on pre and post implementation timing analysis. This is an opportunity to work and interact with accomplished digital and analog circuit designers and timing experts who has built industry leading multi-protocol memory PHYs for over a decade. Desired Qualifications. Prior experience in timing and or RTL design of high-speed interfaces. Prior experience of collaborating with Physical Design teams in multiple successful ASICIP tapeouts. Knowledge of the IPSoC level timing closure flow and methodology. Good command of VerilogSystem Verilog language Command of Simulation, Lint, Synthesis, STA, formal verification, functional coverage, design for test, and design methodologies Ability to handle multiple projectstasks successfully Experience in IPASIC timing constraints generation. Expertise in STA tools and flow Hands on experience in timing constraints generation and management Proficiency in scripting languages (TCL and Perl) Familiarity with synthesis, logic equivalence, DFT and backend related methodology and tools Background in Constraint analysis and debug, using industry standard tools. Understanding and experience in timing closure of various test modes such as scan shift, scan capture, atspeed and BIST testing. Desired skills Knowledge of DDRGDDR DRAM protocol high-speed PHYs Experience designing or integrating IP Experience in high speed and low power digital design using advanced deep micron process. Experience with highly configurable designs

Keywords: HPC Americas Consulting LLC, San Jose , RTL Design Engineer, Engineering , San Jose, California