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Senior Principal Design Engineer

Company: Cadence Design Systems
Location: San Jose
Posted on: November 21, 2020

Job Description:

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are SVG (System Verification Group) We are developing one of the most complex ASIC in the industry dedicated to Emulation. I am sure you heard about the Palladium product family that has been leading the industry for more than 20 years. Palladium platform is used across all major Semiconductor companies in the world (big and small). We are looking to strengthen our team in the US where you will lead our DFT team. You will have a chance to interact with all our R & D team, use our latest and greatest products, work alongside architecture / P & R and frontend teams to develop the next emulation platform. We are a small passionate team, if you like challenges, Palladium is a fully synchronous system with pseudo custom work spanning the full size of our very large die. Responsibilities include, but are not limited to the following: - Lead a team of DFT engineers taking a complex ASIC from architecture all the way through productization. - Oversee DFT Gate Level Simulations work and support RTL/PD engineer to correct DFT violations throughout the flow. - Supervise ATPG patterns development to successfully take our ASIC through production. - Participate in ATE bring up, Silicon Debug and Support in system testing within our labs and partners. Qualifications: - Bachelors in Computer Science or Electrical Engineering + 10 years of related experience, or Masters + 7 years of related experience, or PhD + 5 years of related experience - Experienced with all phases of DFT flow implementation & verification including SCAN, PMBIST, JTAG and other DFTs related logic. - Well versed with SCAN/PMBIST/JTAG Flow co-development and issues encountered at every stage (Synthesis / P & R / Signoff). - Must have experience leading teams of engineers. Were doing work that matters. Help us solve what others cant.

Keywords: Cadence Design Systems, San Jose , Senior Principal Design Engineer, Engineering , San Jose, California

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