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Design Verification Engineer (Minimum 4+ Years of experience)

Company: Mirafra Inc
Location: San Jose
Posted on: March 27, 2020

Job Description:

Role Design Verification Engineer Location San Jose, CA Austin, TX Duration Full Time Key responsibilities include 5 + yearrsquos industry experience in a design verification role Learn the architecture and micro architecture by studying specifications and direct interaction with architects and logic designers of the Coherent fabric and LPDDR memory controller. Develop test plans, test benches and tests, creating sequencers, drivers, checkers, and monitors in a UVM environment. Enhance test benches and tests to achieve coverage goals. Create and support test environments for different design hierarchy levels. Support unit and super-unit debug on simulation platforms. Requirements Minimum requirements BSEE, Computer Engineer or comparable and 2+ years of experience Experienced with verification methodology such as UVMVMMOVM. Developed test plans of complex systems containing multiple state machines and protocol rules. Composed functional coverage assertions, preferably using System Verilog. Preferred candidate will possess the following Exposure to either CPU coherency protocols or DDR memory controllers. ARM-ACE Coherency or LPDDR45 experience would be a bonus. Proficient in System Verilog, C++, and PythonPerl scripting Thanks, Tapan 408-256-7197408-256-6714

Keywords: Mirafra Inc, San Jose , Design Verification Engineer (Minimum 4+ Years of experience), Engineering , San Jose, California

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